This invention relates to CMOS processing and more particularly to using polysilicon as a spacer for implantation.
Complementary Metal Oxide semiconductor (CMOS) technology employs both NMOS (n-channel transistor) and PMOS (p-channel transistor) to form logic elements. The structures and fabrication procedures are described in a book entitled xe2x80x9cVLSI Technology, second edition edited by S. M. Sze, a McGraw Hill Publication (ISBN 0-07-062735-5). In particular, see section 11.4 beginning on page 483. The fabrication process for CMOS is similar to NMOS. Fabrication is also disclosed in many patents such as, for example, Hutter et al. U.S. Pat. No. 4,472,887. This patent is incorporated herein by reference.
The NMOS and PMOS differences occur due to individual doping adjustment for n-channel and p-channel devices. Twin tubs may be formed using lithographic mask process. A composite layer of silicon dioxide SiO2 and Silicon Nitride Si3N4 are defined and silicon is exposed over the n-tub region. Phosphorus is implanted as the n-tub dopant at low energy and enters the exposed silicon; but is masked from the adjacent region by the Silicon Nitride Si3N4. The wafers are then selectively oxidized over the n-tub regions. The nitride is stripped and Boron is implanted for the p-tub. The Boron enters the silicon through the oxide but is masked from the tub by the thicker SiO2 layer. All oxides are then stripped away and the two tubs are driven in by heat. After the tubs are formed, there is the formation of the field oxide and gates. The gate is polysilicon and is formed by a polysilicon deposit on the silicon base of the n-channel and p-channel. Photoresist is placed over the gate regions and etched. It is then necessary to selectively implant the n-channel and p-channel source/drain to form the n+ region for the n-channel and p+ regions for the p-channels. In accordance with one technique the implanting includes implanting Boron non-selectively into all sources and drains. This may then be followed with a selective implant. Phosphorus or Arsenic may be implanted in accordance with one technique into the n-channel source and drain regions at higher dose to overcome the Boron.
In the diffusion of the dopants during normal thermal processing (annealing), the dopants may diffuse closer to the gate than desired causing gate to drain overlap capacitance Cgd to increase more than desired. This causes a delay in the circuit performance. In the above example the Boron diffuses faster so the spacer is on the PMOS alone so the Boron implant is spaced out from the gate to allow more space for the Boron to diffuse. Similar diffusion with other dopants can occur requiring a spacer. It may also be desired to use a spacer for both dopants such as one for Arsenic in this the example.
It is desirable to reduce this capacitance. In a prior art process an additional spacer is placed on the PMOS which is nitride after the gate etch with the additional step of deposition/etch and NMOS mask before the Boron and Arsenic implants are done to form the source and drain.
In accordance with one embodiment of the present invention an improved process is provided wherein polysilicon gates are longer than the final gate length to provide a polysilicon spacer for implanting source and drain.